One process by which a transistor gate is formed includes forming a dummy gate and a dielectric layer around the dummy gate. The dummy gate is then removed, exposing a portion of the underlying substrate through the resulting opening in the dielectric layer. A gate dielectric layer is then formed on the substrate in the opening, and an amorphous silicon layer is deposited on the gate dielectric layer and the sidewalls of the dielectric layer opening. A separate metal layer is then deposited over the amorphous silicon, and an annealing treatment is performed to react the metal with the amorphous silicon to form a metal silicide layer overlying the gate dielectric layer.
However, forming a transistor gate in such manner results in a gate electrode having a work function that is substantially equal to the work function of a polysilicon gate electrode, at least partially due to the existence of an unreacted portion of the amorphous silicon near the gate dielectric layer. In many applications, it is desirable to form gate electrodes of varying work function levels. The remaining amorphous silicon is also highly resistive, and results in an increased effective oxide thickness (EOT). Such a process is also complicated, requiring numerous time- and cost-intensive process steps.